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ltc3553 1 3553fa typical application description micropower usb power manager with li-ion charger, ldo and buck regulator the ltc ? 3553 is a micropower, highly integrated power management and battery charger ic for single-cell li-ion/polymer battery applications. it includes a powerpath manager with automatic load prioritization, a battery charger, an ideal diode and numerous internal protection features. designed speci? cally for usb applica- tions, the ltc3553 power manager automatically limits input current to a maximum of either 100ma or 500ma. battery charge current is automatically reduced such that the sum of the load current and the charge current does not exceed the selected input current limit. the ltc3553 also includes a synchronous buck regulator, a low dropout linear regulator (ldo), and a pushbutton controller. with all supplies enabled in standby mode, the quiescent current drawn from the battery is only 12a. the ltc3553 is avail- able in a 3mm 3mm 0.75mm 20-pin qfn package. battery drain current vs temperature features applications n 12a standby mode quiescent current (all outputs on) n seamless transition between input power sources: li-ion/polymer battery and usb n 240m internal ideal diode provides low loss powerpath? n high ef? ciency 200ma buck regulator n 150ma low dropout (ldo) linear regulator n pushbutton on/off control with system reset n full featured li-ion/polymer battery charger n programmable charge current with thermal limiting n instant-on operation with discharged battery n 3mm 3mm 0.75mm 20-pin qfn package n usb-based handheld products n portable li-ion/polymer based electronic devices n wearable electronics n low power medical devices v bus ntc prog seq hpwr susp ldo_on buck_on stby pbstat on v out chrg bat bvin v inldo ldo ldo_fb sw buck_fb on/off li-ion battery 10f 2.2f 10f 100k 100k digital control t 1.87k 4.7f 2.05m 649k 3.3v 150ma 10pf 10f 332k 649k 1.2v 200ma 3553 ta01a 10h system load 4.35v to 5.5v usb input ltc3553 + temperature (c) C50 C30 C10 30 50 70 90 130 110 10 0 battery drain current (a) 4 6 10 18 16 14 12 8 3553 ta01b 2 buck and ldo on v bat = 3.8v stby = 3.8v regulators load = 0ma only ldo on only buck on buck and ldo off hard reset l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and powerpath, hot swap and bat-track are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6522118, 6700364, 5481178, 6304066, 6570372, 6580258, 7511390 and other patents pending.
ltc3553 2 3553fa pin configuration absolute maximum ratings v bus , v out t < 1ms and duty cycle < 1% .................. C0.3v to 7v steady state ............................................. C0.3v to 6v bat, ntc, chrg , susp , pbstat, on , buck_fb, ldo_fb ................................ C0.3v to 6v buck_on, ldo_on, stby, seq, hpwr, bvin, v inldo , ldo (note 4) .............C0.3v to v cc + 0.3v i bat .............................................................................1a i sw (continuous) .................................................300ma i ldo (continuous) ................................................175ma i chrg , i pbstat .........................................................75ma operating temperature range.................. C40c to 85c junction temperature ........................................... 110c storage temperature range ................... C65c to 125c (notes 1, 2, 3) order information lead free finish tape and reel part marking package description temperature range ltc3553eud#pbf ltc3553eud#trpbf lfyb 20-lead (3mm 3mm) plastic qfn C40c to 85c ltc3553epd#pbf ltc3553epd#trpbf fhst 20-lead (3mm 3mm) plastic utqfn C40c to 85c (obsolete) consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ power manager electrical characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c (note 2), v bus = 5v, v bat = 3.8v, hpwr = susp = buck_on = ldo_on = 0v, r prog = 1.87k, stby = high, unless otherwise noted. symbol parameter conditions min typ max units no-load quiescent currents i batq battery drain current (note 5) buck and ldo shutdown, hard reset buck and ldo shutdown buck and ldo enabled, standby mode buck and ldo enabled buck enabled, ldo shutdown ldo enabled, buck shutdown i out = i sw = i ldo = 0 v bus = 0v, hard reset v bus = 0v v bus = 0v, buck_on = ldo_on = stby = 3.8v v bus = 0v, buck_on = ldo_on = 3.8v, stby = 0v v bus = 0v, buck_on = 3.8v, ldo_on = 0v stby = 0v v bus = 0v, ldo_on = 3.8v, buck_on = 0v, stby = 0v 0.2 3 8 16 6.5 16 2 5 16 35 15 35 a a a a a a i batqc battery drain current, v bus available v bat = v float , timer timed out 5 8 a i busq v bus input current 100ma, 500ma modes charger on timer timed out susp = 5v (suspend mode) 300 150 15 500 350 30 a a a 20 19 18 17 16 7 8 top view 21 gnd ud package 20-lead (3mm 3mm) plastic qfn 9 10 hpwr seq pbstat on ldo_on ntc chrg sw bvin v inldo v bus susp v out bat prog stby buck_on buck_fb ldo_fb ldo 12 11 13 14 15 4 5 3 2 1 6 t jmax = 110c, ja = 70c/w exposed pad (pin 21) is gnd, and must be soldered to pcb gnd
ltc3553 3 3553fa power manager electrical characteristics symbol parameter conditions min typ max units i bvinq bvin input current buck shutdown buck enabled, standby mode buck enabled v bus = 0v, v bvin = 3.8v, i sw = 0 (note 8) buck_on = 0v buck_on = stby = 3.8v buck_on = 3.8v, stby = 0v 0.01 1.5 22 1 3 38 a a a i vinldoq v inldo input current ldo shutdown ldo enabled, standby mode ldo enabled v bus = 0v, v inldo = 3.8v, i ldo = 0 (note 10) ldo_on = 0v ldo_on = stby = 3.8v ldo_on = 3.8v, stby = 0v 0.01 0.1 0.1 1 1 1 a a a input power supply v bus input supply voltage 4.35 5.5 v i bus(lim) total input current hpwr = 0v (100ma) hpwr = 5v (500ma) l l 80 400 90 450 100 500 ma ma v uvlo v bus undervoltage lockout rising threshold falling threshold 3.5 3.8 3.6 3.9 v mv v duvlo v bus to bat differential undervoltage lockout rising threshold falling threshold 0 200 50 300 mv mv r on_ilim input current limit power fet on-resistance (between v bus and v out ) 350 m battery charger v float v bat regulated output voltage 0 t a 85c 4.179 4.165 4.2 4.2 4.221 4.235 v v i chg constant-current mode charge current r prog = 1.87k, 0 t a 85c 380 400 420 ma v prog v prog,trkl prog pin servo voltage prog pin servo voltage in trickle charge v bat < v trkl 1 0.1 v v h prog ratio of i bat to prog pin current 750 ma/ma i trkl trickle charge current v bat < v trkl 30 40 50 ma v trkl trickle charge threshold voltage v bat rising v bat falling 2.6 2.9 2.75 3v v v rechrg recharge battery threshold voltage threshold voltage relative to v float C75 C100 C125 mv t term safety timer termination period timer starts when v bat = v float C 50mv 3.2 4 5 hour t badbat bad battery termination time v bat < v trkl 0.4 0.5 0.63 hour h c/10 end-of-charge indication current ratio (note 6) 0.085 0.1 0.115 ma/ma r on_chg battery charger power fet on-resistance (between v out and bat) i bat = 200ma 220 m t lim junction temperature in constant temperature mode 110 c ntc v cold cold temperature fault threshold voltage rising ntc voltage hysteresis 75 76 1.3 77 %v bus %v bus v hot hot temperature fault threshold voltage falling ntc voltage hysteresis 34 35 1.3 36 %v bus %v bus v dis ntc disable threshold voltage falling ntc voltage hysteresis l 1.2 1.7 50 2.2 %v bus mv i ntc ntc leakage current v ntc = v bus = 5v C50 50 na the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c (note 2), v bus = 5v, v bat = 3.8v, hpwr = susp = buck_on = ldo_on = 0v, r prog = 1.87k, stby = high, unless otherwise noted.
ltc3553 4 3553fa buck regulator electrical characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c (note 2). buck_on = v out = bvin = 3.8v, unless otherwise noted. symbol parameter conditions min typ max units bvin input supply voltage (note 9) l 2.7 5.5 v v out uvlo v out undervoltage lockout v out falling v out rising 2.5 2.6 2.8 2.9 v v f osc oscillator frequency 0.955 1.125 1.295 mhz i buck_fb buck_fb input current (note 8) C0.05 0.05 a r sw_pd sw pull-down in shutdown buck_on = 0v 10 k logic input pin (stby) input high voltage 1.2 v input low voltage 0.4 v input current C1 1 a buck regulator in normal operation (stby low) i lim peak pmos current limit buck_on = 3.8v (note 7) 300 500 650 ma v buck_fb regulated feedback voltage buck_on = 3.8v l 780 800 820 mv d max max duty cycle 100 % r p r ds(on) of pmos i sw = 100ma 1.1 r n r ds(on) of nmos i sw = C100ma 0.7 buck regulator in standby mode (stby high) feedback voltage threshold buck_on = 3.8v, v buck_fb falling l 770 800 820 mv short-circuit current 30 50 100 ma standby mode dropout voltage buck_on = 2.9v, i sw = 10ma, v buck_fb = 0.76v, v out = 2.9v, bvin = 2.9v 50 100 mv power manager electrical characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c (note 2), v bus = 5v, v bat = 3.8v, hpwr = susp = buck_on = ldo_on = 0v, r prog = 1.87k, stby = high, unless otherwise noted. symbol parameter conditions min typ max units ideal diode v fwd forward voltage detection (note 12) 15 mv r dropout diode on-resistance, dropout i out = 200ma, v bus = 0v 240 m i max diode current limit (note 7) 1 a logic inputs (hpwr, susp) v il input low voltage 0.4 v v ih input high voltage 1.2 v r pd internal pull-down resistance 4m logic output ( chrg ) v ol output low voltage i chrg = 5ma 65 250 mv i chrg output hi-z leakage current v bat = 4.5v, v chrg = 5v 0 1 a
ltc3553 5 3553fa symbol parameter conditions min typ max units v inldo input voltage range (note 9) l 1.65 5.5 v v out uvlo v out undervoltage lockout v out falling v out rising 2.5 2.6 2.8 2.9 v v v ldo_fb regulated feedback voltage i ldo = 1ma, stby high or low (note 10) l 780 800 820 mv v ldo_fb line regulation i ldo = 1ma, v inldo = 1.65v to 5.5v (note 10) 0.7 mv/v v ldo_fb load regulation i ldo = 1ma to 150ma (note 10) 0.025 mv/ma i ldo_fb feedback pin input current C50 50 na i ldo_oc available output current l 150 ma i ldo_sc short-circuit output current (note 7) 300 ma v drop dropout voltage (note 13) i ldo = 150ma, v inldo = 3.8v i ldo = 150ma, v inldo = 2.5v i ldo = 75ma, v inldo = 1.8v 160 220 180 260 350 280 mv mv mv t ldo_ss soft-start time 0.2 ms r ldo_pd output pull-down resistance in shutdown ldo_on = 0v 10 k pushbutton interface electrical characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c (note 2). v bat = 3.8v, unless otherwise noted. ldo regulator electrical characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c (note 2). ldo_on = v out = v inldo = 3.8v, stby = 0v, unless otherwise noted. symbol parameter conditions min typ max units pushbutton pin ( on ) v cc_pb pushbutton operating supply range (notes 4 , 9) l 2.7 5.5 v v on _th on threshold rising on threshold falling 0.4 1.2 v v i on on input current v on = v cc (note 4) C1 1 a r pb_pu pushbutton pull-up resistance pull-up to v cc (note 4) 200 400 650 k logic input pins (buck_on, ldo_on, seq) input high voltage input low voltage 1.2 0.4 v v input current C1 1 a status output pin (pbstat) i pbstat pbstat output high leakage current v pbstat = 3v C1 1 a v pbstat pbstat output low voltage i pbstat = 3ma 0.1 0.4 v
ltc3553 6 3553fa note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3553e is tested under pulsed load conditions such that t j t a . the ltc3553e is guaranteed to meet speci? cations from 0c to 85c junction temperature. speci? cations over the C40c to 85c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where ja (in c/w) is the package thermal impedance. note that the maximum ambient temperature consistent with these speci? cations is determined by speci? c operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperatures will exceed 110c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may result in device degradation or failure. note 4: v cc is the greater of v bus or bat. note 5: total battery drain current represents the load a battery will see in application due to quiescent currents drawn by the bat pin (i batq ) plus any current drawn from the v out pin. in applications where the buck input (bvin pin) and ldo input (v inldo pin) are connected to the powerpath output (v out pin), the quiescent currents on bvin and v inldo must be added to i batq to get the actual battery drain current that will be seen in application. note 6: h c/10 is expressed as a fraction of programmed full charge current with speci? ed prog resistor. note 7: the current limit features of this part are intended to protect the ic from short term or intermittent fault conditions. continuous operation above the absolute maximum speci? ed pin current rating may result in device degradation or failure. note 8: buck_fb high, not switching note 9: v out not in uvlo. note 10: measured with the ldo operating in unity-gain, with its output and feedback pins tied together. note 11: see the operation section of this data sheet for detailed explanation of the pushbutton state machine and the effects of each state on regulator and power manager operation. note 12: if v bus < v uvlo then v fwd = 0 and the forward voltage across the ideal diode is equal to its current times r dropout . note 13: dropout voltage is the minimum input to output voltage differential needed for the ldo to maintain regulation at a speci? ed output current. when the ldo is in dropout, its output voltage will be equal to: v inldo C v drop . pushbutton interface electrical characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c (note 2). v bat = 3.8v, unless otherwise noted. symbol parameter conditions min typ max units pushbutton timing parameters (note 11) t on _pbstatl minimum on low time to cause pbstat low on brought low during power-on (pon) or power-up (pup1, pup2) states 50 ms t on _pbstath delay from on high to pbstat high power-on (pon) state, after pbstat has been low for at least t pbstat_pw 900 s t on _pup minimum on low time to enter power-up (pup1 or pup2) state starting in the hard reset (hr) or power-off (poff) states 400 ms t on _hr minimum on low time to hard reset on brought low during the power-on (pon) or power-up (pup1, pup2) states 45 6 s t pbstat_pw pbstat minimum pulse width power-on (pon) or power-up (pup1, pup2) states 40 50 ms t extpwr power-up from usb present to power-up (pup1 or pup2) state starting in the hard reset (hr) or power-off (poff) states 100 ms t pon_up buck_on or ldo_on high to power-on state starting with both buck_on and ldo_on low in the power-off (poff) state 900 s t pon_dis_buck buck_on low to buck disabled 1 s t pon_dis_ldo ldo_on low to ldo disabled 1s t pup power-up (pup1 or pup2) state duration 5 s t pdn power-down (pdn1 or pdn2) state duration 1s
ltc3553 7 3553fa v bus supply current vs temperature v bus supply current vs temperature (suspend mode) battery drain current vs temperature v bus current limit vs temperature typical performance characteristics t a = 25c, unless otherwise speci? ed. temperature (c) C75 200 i bus (a) 300 350 400 C25 25 50 150 3553 g01 250 C50 0 75 100 125 v bus = 5v hpwr = l temperature (c) C75 0 i bus (a) 10 15 25 20 C25 25 50 150 3553 g02 5 C50 0 75 100 125 v bus = 5v temperature (c) C75 0 i bat (a) 2 3 5 4 C25 25 50 150 3553 g04 1 C50 0 75 100 125 v bus = 5v v bat = 3.8v temperature (c) C75 0 i vbus (ma) 200 300 500 400 C25 25 50 3553 g05 100 C50 0 75 100 125 v bus = 5v hpwr = h hpwr = l battery drain current vs temperature (suspend mode) v bus and battery current vs load current battery charge current and voltage vs time r on from v bus to v out vs temperature charge current vs temperature (thermal regulation) temperature (c) C75 C50 C25 25 50 75 100 150 125 0 0.20 r on () 0.30 0.35 0.45 0.50 0.40 3553 g07 0.25 i out = 200ma temperature (c) C50 C30 C10 30 50 70 90 130 110 10 0 battery drain current (a) 4 6 10 18 16 14 12 8 3553 g03 2 buck and ldo on v bat = 3.8v stby = 3.8v regulators load = 0ma only ldo on only buck on buck and ldo off hard reset load current (ma) 0 100 300 500 400 200 C100 current (ma) 100 200 400 600 500 300 3553 g06 0 r prog = 1.87k i vbus i load i bat (charging) i bat (discharging) temperature (c) C75 0 i bat (ma) 160 240 480 400 320 C25 25 50 150 3553 g08 80 C50 0 75 100 125 v bus = 5v hpwr = h r prog = 1.87k time (hour) 0 0 battery current (ma) voltage (v) 200 300 600 500 400 2 4 5 3553 g09 100 0 2 3 6 5 4 1 13 6 7 8 920mahr cell v bus = 5v r prog = 1.87k chrg v bat safety timer termination c/10 i bat
ltc3553 8 3553fa typical performance characteristics battery charge current vs battery voltage forward voltage vs ideal diode current v bus connect waveform v bus disconnect waveform v float load regulation battery regulation (float) voltage vs temperature t a = 25c, unless otherwise speci? ed. i bat (ma) 050 4.192 v float (v) 4.196 4.198 4.204 4.202 4.200 200 150 250 350 450 400 3553 g10 4.194 100 300 v bus = 5v hpwr = h temperature (c) C75 C25 C50 4.150 v float (v) 4.200 4.225 4.250 50 100 125 3553 g11 4.175 25 075 v bus = 5v i bat = 2ma i bat (ma) 0 400 200 0 v fwd (mv) 100 150 250 300 200 1000 1200 3553 g13 50 800 600 v bus = 5v v bus = 0v v bat = 3.8v i ldo = 100ma i buck = 100ma hpwr = high susp = low stby = low 20s/div 5v 3.8v buck (1.2v) v bus v out 0v 3553 g14 ldo (3.3v) v bat = 3.8v i ldo = 100ma i buck = 100ma hpwr = high susp = low stby = low 3553 g15 100s/div 5v 3.8v v bus v bus buck (1.2v) v out v out 0v ldo (3.3v) oscillator frequency vs temperature switching from suspend mode to 500ma mode v bat = 3.75v i out = 50ma r prog = 2k hpwr = high 3553 g17 1ms/div 5v 5v susp v out 0 0 0a 0a i bus 0.5a/div i bat 0.5a/div switching from 100ma mode to 500ma mode v bat = 3.75v i out = 50ma r prog = 2k susp = low 3553 g16 1ms/div 5v hpwr 0 0a 0a i bus 0.5a/div i bat 0.5a/div v bat (v) 2 2.4 3.6 4 3.2 2.8 0 i bat (ma) 200 300 500 400 3553 g12 100 4.4 v bus = 5v hpwr = h r prog = 1.87k temperature (c) C50 C30 C10 30 50 70 90 130 110 10 0.95 oscillator frequency (mhz) 1.05 1.10 1.20 1.30 1.25 1.15 3553 g18 1.00 2.7v 3.8v 5.5v
ltc3553 9 3553fa typical performance characteristics buck regulator burst mode ? operation bvin supply current buck regulator standby mode bvin supply current buck regulator 3.3v output ef? ciency vs load buck switching regulator 1.8v output ef? ciency vs load t a = 25c, unless otherwise speci? ed. buck switching regulator 2.5v output ef? ciency vs load buck regulator 1.2v output ef? ciency vs i load buck load (ma) 0.01 0.1 0 efficiency (%) 70 100 1 10 100 1000 3553 g19 60 50 40 30 20 10 80 90 stby = l 3.8v 5v buck load (ma) 0.01 0.1 0 efficiency (%) 70 100 1 10 100 1000 3553 g22 60 50 40 30 20 10 80 90 stby = l 3.8v 5v bvin supply voltage (v) 2.5 3 4 4.5 5.5 5 3.5 0 bvin supply current (a) 10 15 25 35 30 20 3553 g23 5 no load stby = l C45c 25c 90c bvin supply voltage (v) 2.5 3 4 4.5 5.5 5 3.5 0 bvin supply current (a) 1.0 1.5 2.5 3.0 2.0 3553 g24 0.5 no load stby = h C45c 25c 90c buck load (ma) efficiency (%) 3553 g20 0.01 0.1 100 1000 10 1 0 20 30 80 40 50 60 90 100 70 10 stby = l 3.8v 5v buck load (ma) efficiency (%) 3553 g21 0.01 0.1 100 1000 10 1 0 20 30 80 40 50 60 90 100 70 10 stby = l 3.8v 5v buck regulator short-circuit current vs temperature temperature (c) C75 C50 C25 25 50 75 100 150 125 0 400 short circuit current (ma) 440 460 500 480 3553 g25 420 stby = l buck regulator output transient (stby = high) buck regulator output transient (stby = low) v bus = 0v v bat = 3.8v stby = high v out 50mv/div (ac) buck (1.2v) 10mv/div (ac) 5ma 100a i buck 3553 g26 50s/div burst mode is a registered trademark of linear technology corporation. v bus = 0v v bat = 3.8v stby = low buck (1.2v) 50mv/div (ac) v out 50mv/div (ac) 100ma 1ma i buck 3553 g27 100s/div
ltc3553 10 3553fa buck regulator switch impedance vs temperature typical performance characteristics buck regulator feedback voltage vs output current power-up sequencing with seq low t a = 25c, unless otherwise speci? ed. temperature (c) C75 C50 C25 25 50 75 100 150 125 0 0 switch impedance () 0.4 0.6 1.6 0.8 1.0 1.2 1.4 3553 g28 0.2 pmos nmos bvin = 3.2v stby = l output current (ma) feedback voltage (v) 3553 g29 0.1 1 100 1000 10 0.780 0.790 0.795 0.820 0.800 0.805 0.810 0.815 0.785 3.8v 5v stby = l regulator output transient during stby transition buck regulator dropout voltage in standby mode vs load current load current (ma) 0 5 10 15 20 30 25 0 dropout voltage (mv) 40 60 100 120 140 160 180 200 80 3553 g32 20 C45c 25c 90c bvin = 2.9v buck output 0.5v/div ldo output 1v/div 0v 0v 3553 g30 100s/div front page application circuit buck output 0.5v/div ldo output 1v/div 0v 0v 3553 g33 100s/div front page application circuit power-up sequencing with seq high v bus = 0v v bat = 3.8v buck output 1.2v at 10ma 20mv/div (ac) ldo output 3.3v at 10ma 50mv/div (ac) high low stby 3553 g31 50s/div temperature (c) C50 C30 C10 30 50 70 90 130 110 10 780 feedback voltage (mv) 790 795 820 800 805 810 815 3553 g34 785 v inldo = 2.9v v inldo = 3.8v v inldo = 5v 100a ldo load ldo load (ma) 25 50 75 100 150 125 0 796 ldo output voltage (mv) 798 799 800 801 3553 g35 797 ldo in unity gain v inldo = 3.8v v out = v bat = 3.8v v bus = 0v stby = low v inldo (v) 123 5 4 0 ldo short-circuit current (ma) 100 150 400 200 250 300 350 3553 g36 50 regulated ldo feedback voltage vs temperature ldo load regulation ldo short-circuit current
ltc3553 11 3553fa typical performance characteristics t a = 25c, unless otherwise speci? ed. ldo dropout voltage at v inldo = 3.8v ldo load (ma) 25 50 75 100 150 125 0 0 ldo dropout voltage (mv) 100 150 200 250 300 3553 g37 50 C45c 25c 90c ldo dropout voltage at v inldo = 2.5v ldo load (ma) 25 50 75 100 150 125 0 0 ldo dropout voltage (mv) 100 150 200 250 300 3553 g38 50 C45c 25c 90c ldo load (ma) 15 30 45 60 75 0 0 ldo dropout voltage (mv) 100 150 200 250 300 3553 g39 50 C45c 25c 90c ldo dropout voltage at v inldo = 1.8v v bus = 0v v bat = 3.8v stby = low v out 50mv/div (ac) ldo (3.3v) 50mv/div (ac) 100ma 1ma i ldo 3553 g40 50s/div v bus = 0v v bat = 3.8v stby = high v out 50mv/div (ac) ldo (3.3v) 100mv/div (ac) 100ma 1ma i ldo 3553 g41 50s/div buck output connected to v inldo 5ma ldo load 4.7f ldo output capacitor v bat = 3.8v, v bus = 0v buck output 1.8v 10mv/div (ac) ldo output 1.2v 10mv/div (ac) 3553 g42 10s/div ldo output transient (stby = low) ldo output transient (stby = high) ldo rejection of buck output ripple
ltc3553 12 3553fa hpwr (pin 1): high power logic input. when this pin is low the input current limit is set to 100ma and when this pin is driven high it is set to 500ma. the susp pin needs to be low for the input current limit circuit to be enabled. this pin has a conditional internal pull-down resistor when power is applied to the v bus pin. seq (pin 2): regulator power-up sequence select. while in the power off or hard reset states, a button press or application of usb bus power causes the pushbutton in- terface to temporarily enable both regulators. the state of the seq pin determines which regulator is enabled before the other. if seq is low, the buck regulator is enabled ? rst. if seq is high, the ldo regulator is enabled ? rst. the second regulator is enabled once the feedback voltage of the ? rst regulator nears regulation. the seq pin must be tied to either v out or ground. pbstat (pin 3): p u s h b u t t o n s t a t u s . t h i s o p e n - d r a i n o u t p u t is a debounced and buffered version of the on pushbutton input. it may be used to interrupt a microprocessor. on (pin 4): pushbutton input. weak internal pull-up forces a high state if on is left ? oating. a normally open pushbutton is connected from on to ground to force a low state on this pin. ldo_on (pin 5): logic input enables the low dropout (ldo) regulator. this pin must be driven to a valid logic level. do not ? oat this pin. stby (pin 6): standby mode. when this pin is driven high, the buck and ldo regulator quiescent current is reduced to very low levels, while still maintaining output voltage regulation. in this mode, the buck regulator is limited to 10ma maximum load current, and the ldo regulators r e s p o n s e t o l i n e a n d l o a d t r a n s i e n t s i s s l o w e r. t h i s p i n m u s t be driven to a valid logic level. do not ? oat this pin. buck_on (pin 7): logic input enables the buck regula- tor. this pin must be driven to a valid logic level. do not ? oat this pin. buck_fb (pin 8): feedback input for the buck regulator. this pin servos to a ? xed voltage of 0.8v when the control loop is complete. ldo_fb (pin 9): feedback input for the low dropout regulator. this pin servos to a ? xed voltage of 0.8v when the control loop is complete. ldo (pin 10): low dropout (ldo) linear regulator out- put. this pin should be bypassed with a low impedance multilayer ceramic capacitor. v inldo (pin 11): power input pin for the ldo regulator. this pin is to be connected to v out or any supply volt- age below v out , such as the buck regulator output. this pin should be bypassed with a low impedance multilayer ceramic capacitor. bvin (pin 12): power input for the buck regulator. it is recommended that this pi n be connected to the v out pin. it should be bypassed with a low impedance multilayer ceramic capacitor. sw (pin 13): power transmission (switch) pin for the buck regulator. chrg (pin 14): open-drain charge status output. this pin indicates the status of the battery charger. it is internally pulled low while charging. once the battery charge cur- rent reduces to less than one-tenth of the programmed charge current, this pin goes into a high impedance state. an external pull-up resistor and/or led is required to provide indication. ntc (pin 15): the ntc pin connects to a batterys therm- istor to determine if the battery is too hot or too cold to charge. if the batterys temperature is out of range, charging is paused until it drops back into range. a low drift bias resistor is required from v bus to ntc and a thermistor is required from ntc to ground. if the ntc function is not desired, the ntc pin should be grounded. prog (pin 16): charge current program and charge current monitor pin. connecting a resistor from prog to ground programs the charge current as given by: i chg (a) = 750v r prog if suf? cient input power is available in constant-current mode, this pin servos to 1v. the voltage on this pin always represents the actual charge current. pin functions
ltc3553 13 3553fa pin functions bat (pin 17): single-cell li-ion battery pin. depending on available power and load, a li-ion battery on bat will either deliver system power to v out through the ideal diode or be charged from the battery charger. v out (pin 18) : output voltage of the powerpath controller and input voltage of the battery charger. the majority of the portable products should be powered from v out . the ltc3553 will partition the available power between the external load on v out and the internal battery charger. priority is given to the external load and any extra power is used to charge the battery. an ideal diode from bat to v out ensures that v out i s p o w e r e d e v e n i f t h e l o a d e x c e e d s the allotted input current from v bus or if the v bus power source is removed. v out should be bypassed with a low impedance multilayer ceramic capacitor. susp (pin 19): suspend mode logic input. if this pin is driven high the input current limit path is disabled. in this state the circuit draws negligible power from the v bus pin. any load at the v out pin is provided by the battery through the internal ideal diode. when this input is grounded, the input current limit will be set to desired value as determined by the state of the hpwr pin. this pin has a conditional internal pull-down resistor when power is applied to the v bus pin. v bus (pin 20): usb input voltage. v bus will usually be connected to the usb port of a computer or a dc output wall adapter. v bus should be bypassed with a low imped- ance multilayer ceramic capacitor. gnd (exposed pad pin 21): ground. the exposed package pad is ground and must be soldered to the pc board for proper functionality and for maximum heat transfer.
ltc3553 14 3553fa block diagram 0.8v 150ma ldo en stby input current limit cc/cv charger battery temp monitor pushbutton interface and sequence logic 1.125mhz oscillator charge status 0.8v osc v bus v out bat prog sw buck_fb v inldo ldo ldo_fb hpwr susp ntc extpwr uvlo stby gnd 3553 bd1 buck_on ldo_on pbstat on chrg 200ma buck dc/dc en stby seq 20 18 17 16 bvin 12 13 8 11 10 9 1 19 15 14 6 21 7 5 3 4 2
ltc3553 15 3553fa introduction the ltc3553 is a highly integrated power management ic that includes the following features: powerpath controller battery charger ideal diode pushbutton controller 200ma buck regulator 150ma low dropout (ldo) linear regulator designed speci? cally for usb applications, the powerpath controller incorporates a precision input current limit which communicates with the battery charger to ensure that input current never violates the usb speci? cations. the ideal diode from bat to v out guarantees that ample power is always available to v out even if there is insuf? cient or absent power at v bus . the ltc3553 also includes a pushbutton input to control the two regulators and system reset. the constant-frequency current mode step-down switching regulator provides 200ma and supports 100% duty cycle operation as well as burst mode operation for high ef? ciency at light load. no external compensation components are required for the switching regulator. the ldo can deliver up to 150ma, and is stable with a ceramic output capacitor of at least 1f. for application ? exibility, the ldos power input pin, v inldo , is independent of the bucks bvin pin. the ldo can be powered by the buck output or be driven by the powerpath v out . either regulator can be programmed for a minimum output voltage of 0.8v and can be used to power a microcontroller core, microcontroller i/o, memory or other logic circuitry. the buck regulator operates at 1.125mhz. both regulators include a low power standby mode which can be used to power essential keep-alive circuitry while draining ultralow current from the battery for extended battery life. usb powerpath controller the input current limit and charger control circuits of the ltc3553 are designed to limit input current as well as control battery charge current as a function of i vout . v out drives the combination of the external load, the buck and ldo regulators and the battery charger. if the combined load does not exceed the programmed input current limit, v out w i l l b e c o n n e c t e d t o v bus through an internal 350m p-channel mosfet. if the combined load at v out exceeds the programmed input current limit, the battery charger will reduce its charge current by the a m o u n t n e c e s s a r y t o e n a b l e t h e e x t e r n a l l o a d t o b e s a t i s ? ed while maintaining the programmed input current. even if the battery charge current is set to exceed the allowable usb current, the average input current usb speci? cation will not be violated. furthermore, load current at v out will always be prioritized and only excess available current will be used to charge the battery. the input current limit is programmed by the hpwr and susp pins. if susp pin set high, the input current limit is disabled. if susp pin is low, the input current limit is enabled. hpwr pin selects between 100ma input current limit when it is low and 500ma input current limit when it is high. ideal diode from bat to v out the ltc3553 has an internal ideal diode from bat to v out designed to respond quickly whenever v out drops below bat. if the load increases beyond the input current limit, additional current will be pulled from the battery via the ideal diode. furthermore, if power to v bus (usb) is removed, then all of the application power will be provided by the battery via the ideal diode. the ideal diode is fast enough to keep v out from dropping signi? cantly with just the recommended output capacitor. the ideal diode consists of a precision ampli? er that enables an on-chip p-channel operation simpli? ed powerpath block diagram 100ma/500ma input current limit cc/cv charger 15mv ideal 3553 f01a + ? v out 18 v bus 20 bat 17
ltc3553 16 3553fa mosfet whenever the voltage at v out is approximately 15mv (v fwd ) below the voltage at bat. the resistance of the internal ideal diode is approximately 240m. suspend mode when the susp pin is pulled high the ltc3553 enters suspend mode to comply with the usb speci? cation. in this mode, the power path between v bus and v out is put in a high impedance state to reduce the v bus input current to 15a. the system load connected to v out is supplied through the ideal diode connected to bat. v bus undervoltage lockout (uvlo) and undervoltage current limit (uvcl) an internal undervoltage lockout circuit monitors v bus and keeps the input current limit circuitry off until v bus rises above the rising uvlo threshold (3.8v) and at least 200mv above v bat . hysteresis on the uvlo turns off the input current limit circuitry if v bus drops below 3.6v or within 50mv of v bat . when this happens, system power at v out will be drawn from the battery via the ideal diode. to minimize the possibility of oscillation in and out of uvlo when using resistive input supplies, the input current limit is reduced as v bus falls below 4.45v typical. battery charger the ltc3553 includes a constant-current/constant-volt- age battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out of temperature charge pausing. when a battery charge cycle begins, the battery charger ? rst determines if the battery is deeply discharged. if the battery voltage is below v trkl , typically 2.9v, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. if the low voltage persists for more than 1/2 hour, the battery charger automatically terminates. once the battery voltage is above 2.9v, the battery charger begins charging in full power constant current mode. the current delivered to the battery will try to reach 750v/r prog . depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed current. the ex ternal load will always be prioritized over the battery charge current. the usb cur- rent limit programming will always be observed and only additional current will be available to charge the battery. when system loads are light, battery charge current will be maximized. charge termination the battery charger has a built-in safety timer. when the battery voltage approaches the ? oat voltage, the charge current begins to decrease as the ltc3553 enters con- stant-voltage mode. once the battery charger detects that it has entered constant-voltage mode, the four hour safety timer is started. after the safety timer expires, charging of the battery will terminate and no more current will be delivered to the battery. automatic recharge after the battery charger terminates, it will remain off drawing only microamperes of current from the battery. if the portable product remains in this state long enough, the battery will eventually self discharge. to ensure that the battery is always topped off, a charge cycle will au- tomatically begin when the battery voltage falls below v rechrg (typically 4.1v). in the event that the safety timer is running when the battery voltage falls below v rechrg , the timer will reset back to zero. to prevent brief excur- sions below v rechrg from resetting the safety timer, the battery voltage must be below v rechrg for approximately 2ms. the charge cycle and safety timer will also restart if the v bus uvlo cycles low and then high (e.g., v bus , is removed and then replaced). charge current the charge current is programmed using a single resis- tor from prog to ground. 1/750th of the battery charge current is delivered to prog which will attempt to servo to 1.000v. thus, the battery charge current will try to reach 750 times the current in the prog pin. the program resistor and the charge current are calculated using the following equations: r prog = 750v i chg ,i chg = 750v r prog operation
ltc3553 17 3553fa in either the constant-current or constant-voltage charg- ing modes, the prog pin voltage will be proportional to the actual charge current delivered to the battery. there- fore, the actual charge current can be determined at any time by monitoring the prog pin voltage and using the following equation: i bat = v prog r prog ? 750 in many c ases, the ac tual bat ter y charge current, i bat , will be lower than i chg due to limited input current available and prioritization with the system load drawn from v out . thermal regulation to prevent thermal damage to the ic or surrounding components, an internal thermal feedback loop will automatically decrease the programmed charge current if the die temperature rises to approximately 110c. thermal regulation protects the ltc3553 from excessive temperature due to high power operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damaging the ltc3553 or external components. the bene? t of the ltc3553 thermal regula- tion loop is that charge current c an be se t according to the d e s i r e d c h a r g e r a t e r a t h e r t h a n w o r s t - c a s e c o n d i t i o n s w i t h the assurance that the battery charger will automatically reduce the current in worst-case conditions. charge status indication the chrg pin indicates the status of the battery charger. an open-drain output, the chrg pin can drive an indicator led through a current limiting resistor for human interfacing or simply a pull-up resistor for microprocessor interfacing. when charging begins, chrg is pulled low and remains low for the duration of a normal charge cycle. when charg- ing is complete, i.e., the charger enters constant-voltage mode and the charge current has dropped to one-tenth of the programmed value, the chrg pin is released (high impedance). the chrg pin does not respond to the c/10 threshold if the ltc3553 reduces the charge current due to excess load on the v out pin. this prevents false end of charge indications due to insuf? cient power available to the battery charger. even though charging is stopped during an ntc fault the chrg pin will stay low indicating that charging is not complete. battery charger stability considerations the ltc3553s battery charger contains both a constant- voltage and a constant-current control loop. the constant- voltage loop is stable without any compensation when a battery is connected with low impedance leads. excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1f from bat to gnd. furthermore, a 100f 1210 ceramic capacitor in series with a 0.3 resistor from bat to gnd is required to keep ripple voltage low if operation with the battery disconnected is allowed. high value, low esr multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. ceramic capacitors up to 22f may b e u s e d i n p a r a l l e l w i t h a b a t t e r y, b u t l a r g e r c e r a m i c s s h o u l d be decoupled with 0.2 to 1 of series resistance. in constant-current mode, the prog pin is in the feed- back loop rather than the battery voltage. because of the additional pole created by any prog pin capacitance, capacitance on this pin must be kept to a minimum. with no additional capacitance on the prog pin, the battery charger is stable with program resistor values as high as 25k. however, additional capacitance on this node reduces the maximum allowed program resistor. the pole frequency at the prog pin should be kept above 100khz. therefore, if the prog pin has a parasitic capacitance, c prog , the following equation should be used to calculate the maximum resistance value for r prog : r prog 1 2 ? 100khz ? c prog operation
ltc3553 18 3553fa ntc thermistor the battery temperature is measured by placing a nega- tive temperature coef? cient (ntc) thermistor close to the battery pack. to use this feature connect the ntc therm- istor, r ntc , between the ntc pin and ground and a bias resistor, r nom , from v bus to ntc, as shown in figure 1. r nom should be a 1% resistor with a value equal to the value of the chosen ntc thermistor at 25c (r25). the ltc3553 will pause charging when the resistance of the ntc thermistor drops to 0.54 times the value of r25 or approximately 54k (for a vishay curve 1 thermistor, this corresponds to approximately 40c). if the battery charger is in constant-voltage mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. as the temperature drops, the resistance of the ntc thermistor rises. the ltc3553 is also designed to pause charging when the value of the ntc thermistor increases to 3.17 times the value of r25. for a vishay curve 1 thermistor this resistance, 317k, corresponds to approximately 0c. the hot and cold comparators each have approximately 3c of hysteresis to prevent oscillation about the trip point. alternate ntc thermistors and biasing the ltc3553 provides temperature quali? ed charging if a grounded thermistor and a bias resistor are connected to ntc. by using a bias resistor whose value is equal to the room temperature resistance of the thermistor (r25) the upper and lower temperatures are preprogrammed to approximately 40c and 0c, respectively (assuming a vishay curve 1 thermistor). the upper and lower temperature thresholds can be adjusted by either a modi? cation of the bias resistor value or by adding a second adjustment resistor to the circuit. if only the bias resistor is adjusted, then either the upper or the lower threshold can be modi? ed but not both. the other trip point will be determined by the characteristics of the thermistor. using the bias resistor in addition to an adjustment resistor, both the upper and the lower tem- perature trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. examples of each technique are given below. ntc thermistors have temperature characteristics which are indicated on resistance-temperature conversion ta- bles. the vishay-dale thermistor nths0603n011-n1003f, used in the following examples, has a nominal value of 100k and follows the vishay curve 1 resistance-tempera- ture characteristic. in the explanation below, the following notation is used. r25 = value of the thermistor at 25c r ntc|cold = value of thermistor at the cold trip point r ntc|hot = value of the thermistor at the hot trip point r cold = ratio of r ntc|cold to r25 r hot = ratio of r ntc|hot to r25 r nom = primary thermistor bias resistor (see figure 2) r1 = optional temperature range adjustment resistor (see figure 2) operation figure 1. typical ntc thermistor circuit C + C + r nom 100k r ntc 100k ntc v bus ntc_enable 3553 f01 ntc block too_cold too_hot 0.76 ? v bus (ntc rising) 0.35 ? v bus (ntc falling) 0.017 ? v bus (ntc falling) C + 20 15
ltc3553 19 3553fa by using a bias resistor, r nom , different in value from r25, the hot and cold trip points can be moved in either direction. the temperature span will change somewhat due to the nonlinear behavior of the thermistor. the following equations can be used to easily calculate a new value for the bias resistor: r nom = r hot 0.53 8 ?r25 r nom = r cold 3.17 ?r25 where r hot and r cold are the resistance ratios at the de- sired hot and cold trip points. note that these equations are linked. therefore, only one of the two trip points can be independently set, the other is determined by the de- fault ratios designed in the ic. consider an example where a 60c hot trip point is desired. from the vishay curve 1 r-t characteristics, r hot is 0.2488 at 60c. using the above equation, r nom should be set to 46.4k. with this value of r nom , the cold trip point is about 16c. notice that the span is now 44c rather than the previous 40c. this is due to the decrease in tem- perature gain of the thermistor as absolute temperature increases. the upper and lower temperature trip points can be in- dependently programmed by using an additional bias resistor as shown in figure 2. the following formulas can be used to compute the values of r nom and r1: r nom = r cold ?r hot 2.714 ?r25 r1 = 0.536 ? r nom ?r hot ?r25 for example, to set the trip points to 0c and 45c with a vishay curve 1 thermistor choose: r nom = 3.266 ? 0.436 8 2.714 ? 100k = 104.2k the nearest 1% value is 105k: r1 = 0.536 ? 105k C 0.4368 ? 100k = 12.6k the nearest 1% value is 12.7k. the ? nal solution is shown in figure 2 and results in an upper trip point of 45c and a lower trip point of 0c. operation figure 2. ntc thermistor circuit with additional bias resistor C + C + r nom 105k r ntc 100k r1 12.7k ntc v bus ntc_enable 3553 f02 too_cold too_hot 0.76 ? v bus (ntc rising) 0.35 ? v bus (ntc falling) 0.017 ? v bus (ntc falling) C + 20 15 the trip points for the ltc3553s temperature quali? ca- tion are internally programmed at 0.35 ? v bus for the hot threshold and 0.76 ? v bus for the cold threshold. therefore, the hot trip point is set when: r ntc|hot r nom + r ntc|hot ?v bus = 0.35 ? v bus and the cold trip point is set when: r ntc|cold r nom + r ntc|cold ?v bus = 0.76 ? v bus solving these equations for r ntc|cold and r ntc|hot results in the following: r ntc|hot = 0.538 ? r nom and r ntc|cold = 3.17 ? r nom by setting r nom equal to r25, the above equations result in r hot = 0.538 and r cold = 3.17. referencing these ratios to the vishay resistance-temperature curve 1 chart gives a hot trip point of about 40c and a cold trip point of about 0c. the difference between the hot and cold trip points is approximately 40c.
ltc3553 20 3553fa operation buck regulator introduction the ltc3553 includes a constant-frequency current- mode 200ma buck regulator. at light loads, the regulator automatically enters burst mode operation to maintain high ef? ciency. applications with a near-zero-current sleep or memory keep-alive mode can command the ltc3553 buck regula- tor into a standby mode that maintains output regulation while drawing only 1.5a quiescent current. load capability drops to 10ma in this mode. the buck regulator is enabled, disabled and sequenced through the pushbutton interface (see the pushbutton interface section for more information). it is recommended that the buck regulator input supply (bvin) be connected to the system supply pin (v out ). this is recommended because the undervoltage lockout circuit on the v out pin (v out uvlo) disables the buck regulator when the v out voltage drops below the v out uvlo threshold. if driv- ing the buck regulator input supply from a voltage other than v out , the regulator should not be operated outside its speci? ed operating voltage range as operation is not guaranteed beyond this range. output voltage programming figure 3 shows the buck regulator application circuit. the output voltage for the buck regulator is programmed using a resistor divider from the buck regulator output connected to the feedback pin (buck_fb) such that: v buck = 0. 8 v? r1 r2 + 1 ? ? ? ? ? ? typical values for r1 can be as high as 2.2m. (r1 + r2) can be as high as 3m. the capacitor c fb cancels the pole created by feedback resistors and the input capacitance of the buck_fb pin and also helps to improve transient response for output voltages much greater than 0.8v. a variety of capacitor sizes can be used for c fb but a value of 10pf is recommended for most applications. experimentation with capacitor sizes between 2pf and 22pf may yield improved transient response. normal buck operating mode (stby pin low) in normal mode (stby pin low), the buck regulator per- forms as a traditional constant-frequency current mode switching regulator. switching frequency is determined by an internal oscillator which operates at 1.125mhz. an internal latch is set at the start of every oscillator cycle, turning on the main p-channel mosfet switch. during each cycle, a current comparator compares the inductor current to the output of an error ampli? er. the output of the current comparator resets the internal latch, which causes the main p-channel mosfet switch to turn off and the n-channel mosfet synchronous recti? er to turn on. the n-channel mosfet synchronous recti? er turns off at the end of the clock cycle, or when the current through the n-channel mosfet synchronous recti? er drops to zero, whichever happens ? rst. via this mechanism, the error ampli? er adjusts the peak inductor current to deliver the required output power. all necessary compensation is internal to the buck regulator requiring only a single ceramic output capacitor for stability. at light load and no-load conditions, the buck automatically switches to a power-saving hysteretic control algorithm that operates the switches intermittently to minimize switching losses. known as burst mode operation, the figure 3. buck regulator application circuit 3553 f03 0.8v v in c fb c out v buck mp mn gnd buck_fb r1 sw l pwm control en stby r2
ltc3553 21 3553fa buck cycles the power switches enough times to charge the output capacitor to a voltage slightly higher than the regulation point. the buck then goes into a reduced quiescent current sleep mode. in this state, power loss is minimized while the load current is supplied by the output capacitor. whenever the output voltage drops below a predetermined value, the buck wakes from sleep and cycles the switches again until the output capacitor voltage is once again slightly above the regulation point. sleep time thus depends on load current, since the load current determines the discharge rate of the output capacitor. standby mode buck operation (stby pin high) there are situations where even the low quiescent current of burst mode operation is not low enough. for instance, in a static memory keep alive situation, load current may fall well below 1a. in this case, the 22a typical bvin quiescent current in burst mode operation becomes the main factor determining battery run time. standby mode cuts bvin quiescent current down to just 1.5a, greatly extending battery run time in this essen- tially no-load region of operation. the application circuit commands the ltc3553 into and out of standby mode via the stby pin logic input. bringing the stby pin high places the regulator into standby mode, while bringing it low returns it to burst mode operation. in standby mode, buck load capability drops to 10ma. in standby mode, the buck regulator operates hyster- etically. when the buck_fb pin voltage falls below the internal 0.8v reference, a current source from bvin to sw turns on, delivering current through the inductor to the switching regulator output capacitor and load. when the fb pin voltage rises above the reference plus a small hysteresis voltage, that current is shut off. in this way, output regulation is maintained. since the power transfer from bvin to sw is through a high impedance current source rather than through a low impedance mosfet switch, power loss scales with load current as in a linear low dropout (ldo) regulator, rather than as in a switching regulator. for near-zero load condi- tions where regulator quiescent current is the dominant power loss, standby mode is ideal. but at any appreciable load current, burst mode operation yields the best overall conversion ef? ciency. shutdown the buck regulator is shut down and enabled via the pushbutton interface. in shutdown, it draws only a few nanoamps of leakage current from the bvin pin. it also pulls down on its output with a 10k resistor from its switch pin to ground. dropout operation it is possible for the buck regulators input voltage to fall near or below its programmed output voltage (e.g., a bat- ter y voltage of 3.4v with a programmed output voltage of 3.3v). when this happens, the pmos switch duty cycle increases to 100%, keeping the switch on continuously. known as dropout operation, the output voltage equals the regulators input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. soft-start operation in normal operating mode, soft-start works by gradually increasing the maximum allowed peak inductor current for the buck regulator over a 500s period. this allows the output to rise slowly, helping minimize the inrush current needed to charge up the output capacitor. a soft-start cycle occurs whenever the buck is enabled. soft-start occurs only in normal operation, but not in standby mode. standby mode operation is already in- herently current-limited, since the regulator works by intermittently turning on a current source from bvin to sw. changing the state of the stby pin while the regu- lators are operating doesnt trigger a new soft-start cycle, to avoid glitching the outputs. inductor selection many different sizes and shapes of inductors are avail- able from numerous manufacturers. choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler. operation
ltc3553 22 3553fa inductor value should be chosen based on the desired output voltage. see table 1. table 3 shows several induc- tors that work well with the step-down switching buck regulator. these inductors offer a good compromise in current rating, dcr and physical size. consult each manu- facturer for detailed information on their entire selection of inductors. larger value inductors reduce ripple current, which improves output ripple voltage. lower value inductors result in higher ripple current and improved transient response time, but will reduce the available output cur- rent. to maximize ef? ciency, choose an inductor with a low dc resistance. choose an inductor with a dc current rating at least 1.5 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. if output short circuit is a possible condition, the induc- tor should be rated to handle the maximum peak current speci? ed for the buck converter. different core materials and shapes will change the size/current and price/current relationship of an induc- tor. toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. inductors that are very thin or have a very small volume typically have much higher core and dcr losses, and will not give the best ef- ? ciency. the choice of which style inductor to use often depends more on the price versus size, performance and any radiated emi requirements than on what the buck requires to operate. the inductor value also has an effect on burst mode operation. lower inductor values will cause burst mode switching frequency to increase. input/output capacitor selection low esr (equivalent series resistance) ceramic capaci- tors should be used at the buck output as well as at the buck input supply. only x5r or x7r ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. for good transient response and stability the output capacitor should retain at least 4f of capacitance over operating temperature and bias voltage. generally, a good starting point is to use a 10f output capacitor. operation table 3. recommended inductors for the buck regulator inductor part no. l (h) max i dc (a) max dcr () size (l w h) (mm) manufacturer 1117as-4r7m 1117as-6r8m 1117as-100m 4.7 6.8 10 0.64 0.54 0.45 0.18* 0.250* 0.380* 3.0 2.8 1.0 toko www.toko.com cdrh2d11bnp-4r7n cdrh2d11bnp-6r8n cdrh2d11bnp-100n 4.7 6.8 10 0.7 0.6 0.48 0.248 0.284 0.428 3.0 3.0 1.2 sumida www.sumida.com sd3112-4r7-r sd3112-6r8-r sd3112-100-r 4.7 6.8 10 0.8 0.68 0.55 0.246* 0.291* 0.446* 3.1 3.1 1.2 cooper www.cooperet.com epl2014-472ml_ epl2014-682ml_ epl2014-103ml_ 4.7 6.8 10 0.88 0.8 0.6 0.254 0.316 0.459 2.0 1.8 1.4 coilcraft www.coilcraft.com * = typical dcr table 2. ceramic capacitor manufacturers avx www.avxcorp.com murata www.murata.com taiyo yuden www.t-yuden.com vishay siliconix www.vishay.com tdk www.tdk.com table 1. choosing the inductor value desired output voltage recommended inductor value 1.8v or less 10h 1.8v to 2.5v 6.8h 2.5v to 3.3v 4.7h
ltc3553 23 3553fa the switching regulator input supply should be bypassed with a 2.2f capacitor. consult with capacitor manufac- turers for detailed information on their selection and speci? cations of ceramic capacitors. many manufacturers now offer very thin (<1mm tall) ceramic capacitors ideal for use in height-restricted designs. table 2 shows a list of several ceramic capacitor manufacturers. low dropout linear regulator (ldo) the ldo regulator supports a load of up to 150ma. the ldo takes power from the v inldo pin and drives the ldo output pin with the goal of bringing the ldo_fb feedback pin voltage to 0.8v. usually, a resistor divider is connected between the ldos output pin, feedback pin and ground, in order to close the control loop and program the output voltage. for stability, the ldo output must be bypassed to ground with at least a 1f ceramic capacitor. the ldo is enabled or disabled via the pushbutton interface. in cases where the ldo is disabled and the powerpath is actively driving v out , an internal pull-down resistor is switched in to help bring the output to ground. when the ldo is enabled, a soft-start circuit ramps its regulation point from zero to ? nal value over a period of roughly 0.2ms, reducing the required v inldo inrush current. the ldo has two input voltage requirements. the ldos quiescent bias current is supplied through an internal connection to the usb powerpath v out pin. the ldos power input is taken from the v inldo pin. for proper ldo operation, the v inldo pin must be connected to a voltage no greater than v out . for example, v inldo can operation be connected to v out , or to the buck regulator output. connecting v inldo to a voltage exceeding v out may result in loss of regulation. output voltage programming figure 4 shows the ldo regulator application circuit. program the ldo output voltage, v ldo , by choosing r1 and r2 such that: v ldo = 0. 8 v? r1 r2 + 1 ? ? ? ? ? ? standby mode ldo operation (stby pin high) to reduce battery drain current in applications with a static memory keep-alive or other ultralow quiescent current state, the ldo may be placed into standby mode c out ldo output ldo_fb ldo mp 0.8v r2 gnd r1 0 1 3553 f04 ldo enable v inldo figure 4. ldo application circuit
ltc3553 24 3553fa operation (together with the buck regulator). when the stby pin is brought high, ldo bias current is reduced. unlike the buck regulator, the ldos load capability remains unchanged. however, the ldos transient response is slowed, as il- lustrated in figure 5 and figure 6. sirable operation may occur. in applications where the buck input is supplied from other than the v out pin, other measures should be taken to ensure that the buck is not operated outside the speci? ed bvin input supply range, as operation beyond this range is not guaranteed. ldo regulator uvlo considerations the ldo regulators bias current is supplied via an internal connection to the usb powerpath v out pin. the v out uvlo shuts down the ldo when v out drops below about 2.6v in order to prevent the ldo from operating incorrectly due to too low a bias supply voltage. the ldo power input pin, v inldo , can be driven with as little as 1.65v. there is, however, no uvlo to enforce this requirement. it is thus recommended that v inldo be tied to either the buck regulator output (programmed to regulate at least 1.65v), or to the usb powerpath v out pin, to ensure proper operation. pushbutton interface state diagram/operation figure 7 shows the ltc3553 pushbutton state diagram. upon ? rst application of power, v bus or bat, an inter- nal power on reset (por) signal places the pushbutton circuitry into the power-down (pdn1) state. one second figure 7. pushbutton state diagram 3553 f07 pup2 pdn1 pdn2 hrst hrst hrst por uvlo and either buck_on or ldo_on buck_on or ldo_on extpwr or pb400ms 1sec 5sec 5sec 1sec pon pup1 hr uvlo or both buck_on and ldo_on extpwr or pb400ms poff figure 5. ldo load step response in normal operation ldo regulating 3.3v 4.7f output capacitor stby low ldo output voltage ac-coupled 0.1v/div 150ma 5ma i ldo 3553 f05 50s/div ldo regulating 3.3v 4.7f output capacitor stby high ldo output voltage ac-coupled 0.1v/div 150ma 5ma 3553 f06 50s/div i ldo v out undervoltage lockout (v out uvlo) an undervoltage lockout circuit on the usb powerpath v out pin shuts down and prevents both the buck and the ldo from enabling when the v out pin voltage drops below about 2.6v. buck regulator uvlo considerations it is recommended that the buck regulator input supply (bvin pin) be connected directly to the usb powerpath output (v out pin). with this connection, the v out uvlo prevents the buck regulator from operating at low input supply voltages where loss of regulation or other unde- figure 6. ldo load step response in standby mode
ltc3553 25 3553fa after entering the pdn1 state the pushbutton circuitry will transition into the hard reset (hr) state. in the hr state, all supplies are disabled. the powerpath circuitry is placed in an ultralow quiescent state to minimize battery drain. if no external charging supply is present (v bus ) then the ideal diode is shut down, disconnecting v out from bat to further minimize battery drain. the ultra- low power consumption in the hr state makes it ideal for shipping or long term storage, minimizing battery drain. the following events cause the state machine to transition out of hr into the power-up (pup1) state: on input low for 400ms (pb400ms) application of external power (extpwr) u p o n e n t e r i n g t h e p u p 1 s t a t e , t h e p u s h b u t t o n c i r c u i t r y w i l l sequence up the buck and ldo regulators. the state of the seq pin determines which regulator is enabled before the other. if seq is low, the buck regulator is enabled ? rst. if seq is high, the ldo regulator is enabled ? rst. the second regulator is enabled once the feedback voltage of the ? rst regulator nears regulation. the seq pin must be tied to either v out or ground. the buck_on and ldo_on inputs are ignored in the pup1 state. the state machine remains in the pup1 state for ? ve seconds. during the ? ve seconds, the applications microprocessor, powered by the regulators, has time to boot and assert buck_on and/or ldo_on. five seconds after entering the pup1 state, the pushbutton circuitry automatically transitions into the power-on (pon) state. in the pon state, the regulators can be enabled and shut down at any time by the buck_on and ldo_on pins. a h i g h o n b u c k _ o n i s n e e d e d t o k e e p t h e b u c k e n a b l e d , a n d a high on ldo_on is needed to keep the ldo enabled. to remain in the pon state, the application circuit must keep at least one of the buck_on or ldo_on inputs high, else the state machine enters the power-down (pdn2) state. when buck_on and ldo_on are both low, or when v out drops to its undervoltage lockout (v out uvlo) threshold, the state machine will leave the pon state and enter the power-down (pdn2) state. in the power-down state (pdn2), both regulators are kept disabled regard- less of the states of the buck_on and ldo_on pins. the state machine remains in the power-down state for one second, before automatically entering the power-off (poff) state. this one second delay allows all ltc3553 generated supplies time to power down completely before they can be re-enabled. the same events used to exit the hard reset (hr) state are also used to exit the poff state and enter the pup2 state. the pup2 state operates in the same manner as the pup1 state previously described. both regulators remain powered up during the ? ve second power-up (pup1 or pup2) period, regardless of the state of the buck_on and ldo_on inputs. in either the hr or poff states, if either the buck_on or ldo_on pin is driven high, the pushbutton circuitry directly enters the pon state, without passing through the power-up (pup1 or pup2) states. this is because by asserting logic high on the buck_on or ldo_on pins, the application has already told the ltc3553 exactly which regulator(s) to turn on, so there is no need for an inter- mediate pup state in which both regulators are enabled for ? ve seconds. starting from the hr state, bringing the buck_on and/or ldo_on pin(s) high enables the powerpath, if it wasnt already enabled due to v bus power being available. this powers up the v out pin from v bus or bat. when the v out voltage rises above the v out uvlo threshold, the state machine transitions from the hr state into the pon state, allowing the selected regulator(s) to turn on. the hard reset (hrst) event is generated by pressing and holding the pushbutton ( on input low) for ? ve seconds. for a valid hrst event to occur the button press must start in the pup1, pup2 or pon state, but can end in any state. if a valid hrst event is present in pon, pdn2 or poff, then the state machine will transition to the pdn1 state and subsequently transition to the hr state one second later. debounced pushbutton output (pbstat) in the pon, pup1, and pup2 states, the pbstat open- drain output pin outputs a debounced version of the on pushbutton signal. on must be held low for at least 50ms for the pushbutton interface to recognize it and cause operation
ltc3553 26 3553fa pbstat to go low. pbstat goes high impedance when on goes high, except the logic enforces a minimum pulse width of 50ms on pbstat. in the hr, poff, pdn1, and pdn2 states, pbstat remains high impedance regardless of the state of on . power-up via pushbutton press figure 8 shows the ltc3553 powering up through ap- plication of the external pushbutton. for this example the pushbutton circuitry starts in the poff or hr state with a battery connected and both regulators disabled. pushbutton application ( on low) for 400ms transitions the pushbutton circuitry into the pup state and powers up the buck followed by the ldo since the seq pin is low in this e x a m p l e . i f e i t h e r b u c k _ o n o r l d o _ o n i s l o w o r g o e s l o w after the ? ve second period the corresponding regulator(s) will be shut down. in the above example ldo_on is low at the end of the ? ve second period and therefore the ldo is disabled at the end of the ? ve second period. operation the buck_on and ldo_on inputs can be driven via a p/c or by one of the regulator outputs through a high impedance (100k typical) to keep the bucks enabled as described above. pbstat does not go low on initial pushbutton application for power-up, but will go low with subsequent on pushbutton applications in the pup1, pup2 or pon states. power-up via applying external power figure 9 shows the ltc3553 powering up through ap- plication of external power (v bus ). for this example the pushbutton circuitry starts in the poff or hr state with a battery connected and both regulators disabled. 100ms after v bus application the pushbutton circuitry transitions into the pup state and powers up the buck followed by the ldo. the 100ms delay time allows the applied supply to settle. the regulators will stay powered as long as their respective buck_on and ldo_on inputs are driven high before the ? ve second pup period is over. if either buck _ bat v bus on (pb) pbstat buck ldo seq buck_on ldo_on state poff/hr pon pup2/pup1 3553 td02 5s 5s 100ms 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 figure 9. power-up via applying external power bat 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 v bus on (pb) pbstat buck ldo seq buck_on ldo_on state poff/hr pon pup2/pup1 3553 td01 5s 400ms figure 8. power-up via pushbutton press
ltc3553 27 3553fa operation on or ldo_on is low or goes low after the ? ve second period the corresponding regulator(s) will be shut down. in the above example both pins are high at the end of the ? ve second period and therefore both regulator s continue to stay on at the end of the ? ve second period. the buck_on and ldo_on inputs can be driven via a p/c or one of the regulator outputs through a high impedance (100k typ) to keep the regulators enabled as described above. without a battery present, initial power application causes a power-on reset which puts the pushbutton circuitry in the pdn1 state and subsequently the hr state one second later. at this time, if a valid supply voltage is detected at the bus pin (i.e., v bus > v uvlo and v bus C v bat > v duvlo ), the pushbutton circuity immediately enters the pup1 state. for this to work reliably, the bat pin voltage must be kept well-behaved when no bat ter y is connected. ensure this by bypassing the bat pin to gnd with an rc network consisting of a 100f ceramic capacitor in series with 0.3. power-up via asserting the buck_on or ldo_on pins figure 10 shows the ltc3553 powering up by driving buck_on high. for this example the pushbutton circuitry starts in the poff or hr state with a battery connected and all bucks disabled. once buck_on goes high, the pushbutton circuitry enters the pon state and the buck powers up. if ldo_on is brought high at a later time, the ldo will power up. the pushbutton circuitry remains in the pon state. powering up via asserting the buck_on or ldo_on pins i s u s e f u l f o r a p p l i c a t i o n s c o n t a i n i n g a n a l w a y s - o n c t h a t s not powered by the ltc3553 regulators. that c can power bat v bus on (pb) pbstat buck ldo buck_on ldo_on state poff/hr pon 3553 td03 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 figure 10. power-up via asserting the buck_on or ldo_on pins
ltc3553 28 3553fa the application up and down for housekeeping and other activities not needing the users control. power-down by de-asserting both buck_on and ldo_on figure 11 shows the ltc3553 powering down by c/p control. for this example the pushbutton circuitry starts in the pon state with a battery connected and both regula- tors enabled. the user presses the pushbutton ( on low) for at least 50ms, which generates a debounced, low impedance pulse on the pbstat output. after receiving the pbstat signal, the c/p software decides to drive both the buck_on and ldo_on inputs low in order to power down. after the last input goes low, the pushbutton circuitry will enter the pdn2 state. in the pdn2 state a one second wait time is initiated after which the pushbutton circuitry enters the poff state. during this one second time, the on , buck_on and ldo_on inputs as well as external power application are ignored to allow all ltc3553 operation generated supplies to go low. though the above assumes a battery present, the same operation would take place with a valid external supply (v bus ) with or without a bat- tery present. holding on low through the one second power-down period will not cause a power-up event at end of the one second period. the on pin must be brought high following the power-down event and then go low again to establish a valid power-up event. uvlo minimum off-time timing (low battery) figure 12 assumes the battery is either missing or at a voltage below the v out uvlo threshold, and the appli- cation is running via external power (v bus ). a glitch on the external supply causes v out to drop below the v out uvlo threshold temporarily. this v out uvlo condition causes the pushbutton circuitry to transition from the pon state to the pdn2 state. upon entering the pdn2 state the regulators power down together. bat v bus on (pb) pbstat buck ldo seq buck_on ldo_on state pon pon pup2 pdn2 3553 td05 5s 5s 1s, buck powers up ldo powers up 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 figure 12. uvlo minimum off-time timing bat v bus on (pb) pbstat buck ldo buck_on ldo_on state pon poff pdn2 3553 td04 1s c/p control 50ms c/p control 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 figure 11. power-down via de-assertion of buck_on and ldo_on
ltc3553 29 3553fa operation in the typical case where the buck_on and ldo_on pins are driven by logic powered by the regulators, the buck_on and ldo_on pins would also go low, as depicted in figure 12. if the external supply recovers after entering the pdn2 state such that v out is no longer in uvlo, then the ltc3553 will transition back into the pup2 state once the pdn2 one second delay is complete. following the state diagram, the transition from pdn2 to pup2 in this case actually occurs via a brief visit to the poff state. during the brief poff state, the state machine immedi- ately recognizes that valid external power is available and transitions into the pup2 state. entering the pup2 state will cause the buck and ldo to sequence up as described previously in the power-up sections. not depicted here, but in cases where the buck_on or ldo_on pin is driven by a supply other than the ldo or buck that remains high when entering the poff state, then as per the state diagram in figure 7, the pushbutton circuitry will enter the pon state once v out is no longer in uvlo. upon entering the pon state, the enabled regulator(s) will power up. note: if v out drops too low (below about 1.9v) the ltc3553 will see this as a por condition and will enter the pdn1 state rather than the pdn2 state. one second later the part will transition to the hr state. under these conditions an explicit power-up event (such as a pushbutton press) may be required to bring the ltc3553 out of hard reset. hard reset timing hard reset provides an ultralow power-down state for shipping or long term storage as well as a way to power down the application in case of a software lockup. in the case of software lockup, the user can hold the pushbutton ( on low) for ? ve seconds and a hard reset event (hrst) will occur, placing the pushbutton circuitry in the power- d o w n ( p d n1) s t a t e . a t t h i s p o i n t t h e r e g u l a t o r s w i l l b e s h u t down. following a one second power-down period the pushbutton circuitry will enter the hard reset state (hr). holding on low through the one second power-down period will not cause a power-up event at end of the one second period. on must be brought high following the power-down event and then go low again for 400ms to establish a valid power-up event, as shown in figure 13. bat v bus on (pb) pbstat buck ldo seq buck_on ldo_on state pon pup1 hr pdn1 3553 td06 400ms 50ms 5s 1s 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 figure 13. hard reset via holding on low for five seconds
ltc3553 30 3553fa power-up sequencing figure 14 shows the actual power-up sequencing of the ltc3553 with the seq pin held low. the regulators are both initially disabled (0v). once the pushbutton has been applied ( on low) for 400ms, the buck is enabled. the buck slews up and enters regulation. the actual slew rate is con- trolled by the soft start function of the buck in conjunction with output capacitance and load (see the buck regulator operation section for more information). when the buck is within about 8% of ? nal regulation, the ldo is enabled and slews up into regulation. the regulators in figure 14 are slewing up with nominal output capacitors and no- load. adding a load or increasing output capacitance on any of the outputs will reduce the slew rate and lengthen the time it takes the regulator to achieve regulation. figure 15 shows how the regulator start-up sequence is reversed with the seq pin tied high. layout and thermal considerations printed circuit board power dissipation in order to be able to deliver maximum charge current under all conditions, it is critical that the exposed pad on the backside of the ltc3553 package is soldered to a ground plane on the board. correctly soldered to a 2500mm 2 ground plane on a double-sided 1oz copper board, the ltc3553 has a thermal resistance ( ja ) of approximately 70c/w. failure to make good thermal contact between the exposed pad on the backside of the package and an adequately sized ground plane will result in thermal resistances far greater than 70c/w. the conditions that cause the ltc3553 to reduce charge current due to the thermal protection feedback can be approximated by considering the power dissipated in the part. for high charge currents the ltc3553 power dis- sipation is approximately: p d = (v bus Cbat) ? i bat + p d(regs) where p d is the total power dissipated, v bus is the supply voltage, bat is the battery voltage, and i bat is the battery charge current. p d(regs) is the sum of power dissipated on chip by the step-down switching regulators. the power dissipated by the buck regulator can be esti- mated as follows: p d(buck) = (b outx ? i out ) ? (100 - eff)/100 where b outx is the programmed output voltage, i out is the load current and eff is the % ef? ciency which can be measured or looked up on an ef? ciency table for the programmed output voltage. the power dissipated by the ldo regulator can be esti- mated using: p d(ldo) = (v inldo C v ldo ) ? i ldo operation figure 14. power-up sequencing with seq low, front page application circuit figure 15. power-up sequencing with seq high, front page application circuit buck output 0.5v/div ldo output 1v/div 0v 0v 3553 f14 100s/div buck output 0.5v/div ldo output 1v/div 0v 0v 3553 f15 100s/div
ltc3553 31 3553fa where v inldo is the ldo input supply voltage, v ldo is the ldo regulated output voltage, and i ldo is the ldo load current. thus the power dissipated by all regulators is: p d(regs) = p d(buck) + p d(ldo) it is not necessary to perform any worst-case power dis- sipation scenarios because the ltc3553 will automatically reduce the charge current to maintain the die temperature at approximately 110c. however, the approximate ambi- ent temperature at which the thermal feedback begins to protect the ic is: t a = 110c C p d ? ja example: consider the ltc3553 operating from a wall adapter with 5v (v bus ) providing 400ma (i bat ) to charge a li-ion bat ter y at 3.3v (bat ). also assume p d(regs) = 0.3w, so the total power dissipation is: p d = (5v C 3.3v) ? 400ma + 0.3w = 0.98w the ambient temperature above which the ltc3553 will begin to reduce the 400ma charge current, is approxi- mately: t a = 110c C 0.98w ? 70c/w = 41.4c the ltc3553 can be used above 41.4c, but the charge current will be reduced below 400ma. the charge current at a given ambient temperature can be approximated by: p d = (110c C t a ) / ja = (v bus C bat) ? i bat + p d(regs) thus: i bat = [(110c C t a ) / ja C p d(regs) ] (v bus C bat) consider the above example with an ambient tempera- ture of 60c. the charge current will be reduced to approximately: i bat = [(110c C 60c) / 70c/w C 0.3w] / (5v C 3.3v) i bat = (0.71w C 0.3w) / 1.7v = 241ma printed circuit board layout when laying out the printed circuit board, the following list should be followed to ensure proper operation of the ltc3553: 1. the exposed pad of the package (pin 21) should con- nect directly to a large ground plane to minimize thermal and electrical impedance. 2. the traces connecting the regulator input supply pins (bvin and v inldo ) and their respective decoupling capacitors should be kept as short as possible. the gnd side of each capacitor should connect directly to the ground plane of the part. this capacitor provides the ac current to the internal power mosfets and their drivers. it is important to minimize inductance from this capacitor to the pin of the ltc3553. connect bvin to v out and v inldo to its input supply through short low impedance traces. 3. the switching power trace connecting the sw pin to its inductor should be minimized to reduce radiated emi and parasitic coupling. due to the large voltage swing of the switching node, sensitive nodes such as the feedback nodes should be kept far away or shielded from the switching nodes or poor performance could result. 4. connections between the buck regulator inductor and its output capacitor should be kept as short as possible. the gnd side of the output capacitor should connect directly to the thermal ground plane of the part. 5. keep the feedback pin traces (buck_fb and ldo_fb) as short as possible. minimize any parasitic capacitance between the feedback traces and any switching node (i.e., sw and logic signals). if necessary, shield the feedback nodes with a gnd trace. 6. connections between the ltc3553 powerpath pins (v bus and v out ) and their respective decoupling ca- pacitors should be kept as short as possible. the gnd side of these capacitors should connect directly to the ground plane of the part. operation
ltc3553 32 3553fa typical applications v bus ntc prog hpwr susp ldo_on seq stby buck_on pbstat on v out chrg bat bvin v inldo ldo ldo_fb sw buck_fb gnd li-ion battery c1 10f c3 10f r3 r1 100k 20 16 1 19 5 2 6 7 3 4 pb1 8 13 9 10 12 11 17 18 14 15 r prog 1.87k t c4 4.7f c2 2.2f r up1 r up2 2.05m r lo1 649k 3.3v ldo 1.8v c5 10pf c6 10f 332k r lo2 649k 1.2v l1 10h system load 4.35v to 5.5v usb input ltc3553 i/o core pbstat buck_on stby ldo_on susp hpwr 3553 ta02 c memory en r2 100k r3 100k + usb powerpath with li-ion battery (ntc quali? ed charging)
ltc3553 33 3553fa typical applications v bus ntc prog hpwr susp ldo_on seq stby buck_on pbstat on v out chrg bat bvin v inldo ldo ldo_fb sw buck_fb gnd 3 cell alkaline or lithium c1 10f 20 u1 u2 16 1 19 5 2 6 7 3 4 pb1 8 13 9 10 12 11 17 18 14 15 r prog 1.87k c4 4.7f c2 2.2f r up1 1m r up2 590k r lo1 464k 2.5v c5 10pf r4 100k r3 100k c6 10f r lo2 464k 1.8v l1 10h system load 4.35v to 5.5v usb input ltc3553 i/o core pbstat stby en susp hpwr 3553 ta04 c + c3 10f 3-cell alkaline/lithium with powerpath (charger disabled)
ltc3553 34 3553fa package description ud package 20-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1720 rev a) 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.65 0.10 (4-sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 0.20 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 19 20 2 0.40 bsc 0.200 ref 2.10 0.05 3.50 0.05 (4 sides) 0.70 0.05 0.00 ? 0.05 (ud20) qfn 0306 rev a 0.20 0.05 0.40 bsc package outline
ltc3553 35 3553fa information furnished by linear technology corpor ation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s . revision history rev date description page number a 9/10 pd package information removed and ud package information added to data sheet ltc3553eud added and ltc3553epd designated oboslete in order information section note 2 updated pin 21 description updated updated related parts 1 to 16 2 6 13 36
ltc3553 36 3553fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0910 rev a ? printed in usa related parts part number description comments ltc3455 dual dc/dc converter with usb power manager and li-ion battery charger seamless transition between input power sources: li-ion battery, usb and 5v wall adapter, 4mm 4mm qfn-24 package ltc3456 2-cell, multioutput dc/dc converter with usb power manager seamless transition between 2-cell battery, usb and ac wall adapter input power sources, 4mm 4mm qfn-24 package ltc3554 micropower usb power manager with li-ion charger and dual buck regulators pmic with 10a standby mode quiescent current, compact 3mm 3mm 0.55mm 20-pin utqfn package ltc3557 usb power manager with li-ion charger, triple step-down dc/dc regulators triple step-down switching regulators (600ma, 400ma, 400ma); 4mm 4mm qfn-28 package ltc3559 usb charger with dual buck regulators adjustable, synchronous buck converters, 3mm 3mm qfn-16 package ltc4080 500ma standalone charger with 300ma synchronous buck charges single-cell li-ion batteries, timer termination + c/10, thermal regulation, buck output: 0.8v to v bat , buck input v in : 2.7v to 5.5v, 3mm 3mm dfn-10 package v bus ntc prog hpwr susp buck_on seq stby ldo_on pbstat on v out chrg bat bvin sw buck_fb v inldo ldo ldo_fb gnd li-ion battery c1 10f c7 10f r3 r1 100k 20 16 1 19 7 2 6 5 3 4 pb1 9 10 11 8 13 12 17 18 14 15 r prog 1.87k t c4 10f c2 2.2f r up1 r up2 2.05m r lo1 649k 3.3v ldo 1.8v c3 10pf c6 4.7f 332k r lo2 649k 1.2v c5 2.2f l1 4.7h system load 4.35v to 5.5v usb input ltc3553 i/o core pbstat ldo_on stby buck_on susp hpwr 3553 ta03 c memory en r2 100k r3 100k + usb powerpath with li-ion battery (ntc quali? ed charging), and ldo regulator driven by buck regulator typical application

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